A method of automatically arranging a layout of standard cells to prevent latch failures by controlling the internal clock path delay is known. To that end, before starting the automatic layout, some rows of sites for latch cells containing clocks are formed so that no latch cells are arranged in any sites other than those sites. By doing this, the clocks may be wired in the row directions to avoid causing variation in the clock delays by arranging the formed sites in every one or two rows.
On the other hand, it is known that a design support apparatus for semiconductor devices to be used to quickly arrange non-logic cells for reducing electromagnetic radiation from a semiconductor device at the time of designing semiconductor devices. In this design support apparatus for semiconductor devices, a layout section places logic cells and wiring patterns to connect the logic cells. An arranged site detecting section detects an arranged site, which site contains neither the logic cells nor a prohibited area, after a layout is done by the layout section. A non-logic cell pattern store section stores non-logic cell patterns. A prohibited area containing site detecting section detects a prohibited area containing a site, which site contains only a prohibited area. A non-logic cell arranging section arranges non-logic cells on the arranged site. Furthermore, the non-logic cell arranging section compares the arrangement of the prohibited area on the prohibited area containing site with a non-logic cell pattern and arranges non-logic cells only on a site where these do not conflict with each other.    [Patent Document 1] Japanese Laid-Open Patent Publication No. 6-295956    [Patent Document 2] Japanese Laid-Open Patent Publication No. 2001-351979